The present invention relates to an output circuit for a PWM (pulse width modulation) inverter which performs PWM control on the coil voltage of an electric motor.
PWM is an abbreviation for Pulse Width Modulation. The PWM technique is widely used in the field of motor control.
Recently, a PWM inverter rapidly becomes widespread and is widely used in motor control.
FIG. 9 is a block diagram showing the configuration of a usual PWM inverter, and shows an example of a three-phase PWM inverter. In the PWM inverter, generally, the number of output circuits 53 for the PWM inverter varies depending on the phase number of a motor to be controlled, but their fundamental operations are the same with each other.
The configuration of the three-phase PWM inverter will be described with reference to FIG. 9.
First, the fundamental frequency and the effective voltage of a three-phase voltage waveform to be supplied to a motor 60 are set to a frequency voltage setting circuit 58. Next, a PWM control circuit 59 internally generates three-phase PWM signals on the basis of information which is set to the frequency voltage setting circuit 58, and outputs the signals as switching control signals 42, 61, and 62. The switching control signals 42, 61, and 62 are binary signals which respectively instruct that the motor winding terminals 52, 63, and 64 are to be connected to a plus terminal of a main DC power source 14 or a minus terminal thereof. The frequency of the switching control signal 42, 61, or 62 is called a PWM carrier frequency and has a frequency which is usually ten or more times the fundamental frequency of the three-phase voltage waveform which is supplied to the motor 60. Usually, it is often that the fundamental frequency of the three-phase voltage waveform to be supplied to a motor is about 0 to 200 Hz, and the PWM carrier frequency is about 2 to 20 kHz.
A motor release signal 156 is a binary signal which instructs the motor to be set to a free running state or not to be the free running state. The free running state is a state in which all the motor winding terminals 52, 63, and 64 are connected to none of the plus and minus terminals of the main DC power source 14. In a case such as that where a trouble of any kind happens, usually, this state is set so as to protect the motor and a control apparatus.
The output circuits 53 for the PWM inverter are semiconductor switching circuits which control the connection of the motor winding terminal 52, 63, or 64 to the plus or minus terminal of the main DC power source 14 in accordance with the switching control signal 42, 61, or 62. The output circuits 53 are configured so that, when the motor release signal 156 instructs the motor to be set to the free running state, the motor winding terminal 52, 63, or 64 is connected to none of the plus or minus terminal of the main DC power source 14 irrespective of the switching control signal 42, 61, or 62. Usually, the voltage of the main DC power source 14 is often selected to be about DC 140 V which is obtained by rectifying and smoothing AC 100 V, or about DC 280 V which is obtained by rectifying and smoothing AC 200 V.
Hereinafter, the conventional output circuits 53 for the PWM inverter will be described.
FIG. 10 is a circuit diagram showing the configuration of the conventional output circuit 53 for the PWM inverter.
Referring to FIG. 10, a logic inverting circuit 65 inverts positive or negative logic of the switching control signal 42 and outputs an inverted switching signal 80. An AND circuit 157 outputs the result of AND of the motor release signal 156 and the switching control signal 42, as an upper arm switching signal 159. The AND circuit 157 outputs also the result of AND of the motor release signal 156 and the inverted switching signal 80, as a lower arm switching signal 160. On-delay circuits 66 and 67 output upper and lower arm control signals 81 and 82 which are obtained by delaying rise edges of the upper and lower arm switching signals 159 and 160 by an on-delay time TD, respectively.
A base drive circuit 68 causes a power transistor 70 to be turned ON or OFF in accordance with the upper arm control signal 81. A base drive circuit 69 causes a power transistor 71 to be turned ON or OFF in accordance with the lower arm control signal 82. Specifically, when the upper arm control signal 81 is in `H` level, the output transistor of a photocoupler 72 is turned ON. This causes a transistor 74 to be turned ON, so that a transistor 76 is turned OFF, thereby turning ON the power transistor 70. By contrast, when the upper arm control signal 81 is in `L` level, the output transistor of the photocoupler 72 is turned OFF. This causes the transistor 74 to be turned OFF, so that the transistor 76 is turned ON, thereby turning OFF the power transistor 70.
A base drive circuit 69 operates in the strictly same manner as the base drive circuit 68.
Other examples of the base drive circuits 68 and 69 are disclosed in, for example, Japanese utility model unexamined publication No. SHO 57-42589 and Japanese patent unexamined publication No. SHO 59-178980. These examples basically operate in the same manner as the base drive circuits 68 and 69 shown in FIG. 10 and may be replaced with the circuits.
Hereafter, description is made as to operation of the output circuit 53 for the PWM inverter configured above.
First, the case where the motor release signal 156 is in `L` level, namely instructs the motor to be set to the free running state will be considered. Then it will be found that both the power transistors 70 and 71 are in the OFF state irrespective of the level of the switching control signal 42 or in both the cases where the signal is in `L` level and where the signal is in `H` level.
Hereinafter,, the case where the motor release signal 156 is in `H` level or instructs the motor not to be the free running state will be described.
FIG. 11 is a waveform chart showing signals in the output circuit 53 for the PWM inverter of FIG. 10. When the switching control signal 42 is changed from `L` level to `H` level, the on-delay circuit 66 changes the upper arm control signal 81 from `L` level to `H` level with a time delay of the on-delay time TD from the change of the switching control signal 42. When the upper arm control signal 81 is changed to `H` level, the power transistor 70 is turned ON. There exists an operation delay time TX1 between the operations of the base drive circuit 68 and the power transistor 70. The operation delay time TX1 varies depending on changes of temperature of the power transistor 70 and the value of the current passing through the collector, and also on variations and aging of components constituting the base drive circuit 68 and the power transistor 70.
When the switching control signal 42 is changed from `L` level to `H` level, the inverted switching signal 80 is changed from `H` level to `L` level, and the on-delay circuit 67 changes the lower arm control signal 82 to `L` level with a substantially no time delay. When the lower arm control signal 82 is changed to `L` level, the power transistor 71 is turned OFF. There exists an operation delay time TY2 between the operations of the base drive circuit 69 and the power transistor 71. The operation delay time TY2 varies depending on changes of temperature of the power transistor 71 and the value of the current passing through the collector, and also on variations and aging of components constituting the base drive circuit 69 and the power transistor 71.
When the switching control signal 42 is then changed from `H` level to `L` level, the on-delay circuit 66 changes the upper arm control signal 81 to `L` level with a substantially no time delay, so that the power transistor 70 is turned OFF. There exists an operation delay time TY1 between the operations of the base drive circuit 68 and the power transistor 70.
When the switching control signal 42 is changed from `H` level to `L` level, the inverted switching signal 80 is changed from `L` level to `H` level, and the on-delay circuit 67 changes the lower arm control signal 82 from `L` level to `H` level with the time delay TD. When the lower arm control signal 82 is changed to `H` level, the power transistor 71 is turned ON. There exists an operation delay time TX2 between the operations of the base drive circuit 69 and the power transistor 71.
When the operation delay time TX1 or TX2 is compared with the operation delay time TY1 or TY2, usually, the operation delay time TY1 or TY2 tends to be longer than the operation delay time TX1 or TX2. Provided that, considering the worst conditions, the smallest value of the operation delay times TX1 and TX2 is indicated by TXW and the longest value of the operation delay times TY1 and TY2 is indicated by TYW, the on-delay time TD is usually set to have a value which is the sum of a small margin and a value obtained by subtracting TXW from TYW.
In the case where bipolar power transistors are used, the on-delay time TD is set to be about 10 to 50 microseconds. In the case where IGBTs (Insulated gate bipolar transistor) are used, the on-delay time TD is set to be about 5 to 30 microseconds, and, in the case where power MOS-FETs are used, set to be about 2 to 10 microseconds. When the switching control signal 42 is changed from `H` level to `L` level or from `L` level to `H` level, the on-delay time prevents the power transistors 70 and 71 from being simultaneously turned ON so as to short-circuit the plus and minus terminals of the main DC power source 14.
Then the states of the switching control signal 42 and a motor winding terminal voltage 51 will be considered. When the switching control signal 42 is fixed to `L` level, the power transistor 71 is in the ON-state under the state where the power transistor 70 is turned OFF. Therefore, the motor winding terminal 52 is connected to the minus terminal of the main power source 14. When the switching control signal 42 is fixed to `H` level, the power transistor 71 is in the OFF-state under the state where the power transistor 70 is turned ON. Therefore, the motor winding terminal 52 is connected to the plus terminal of the main power source 14.
In the above-described configuration of the prior art, when the switching control signal 42 is changed from `L` level to `H` level or vice versa in the case where the motor release signal 156 is in `H` level or instructs the motor not to be the free running state, both the power transistors 70 and 71 are in the OFF-state for a certain time period. This causes a control error in voltage control of the motor winding terminal 52. The control error produces problems in that the torque and the rotational speed of the motor are varied and that noises and vibrations of the motor are increased in level.
These problems will be described in more detail.
Referring to FIG. 10 and FIG. 11, when the switching control signal 42 is changed from `L` level to `H` level or vice versa, a power transistor which has been in the ON-state is first turned OFF and that which has been in the OFF-state is then turned ON. During a time period, therefore, both the power transistors 70 and 71 are in the OFF-state. This state is called the floating state, and this time period is called the floating time period TZ. Usually, the floating time period TZ is often about 1/2 to 2/3 of the on-delay time TD.
Originally, in the PWM control of a motor, for example, the motor winding terminal 52 is alternatingly connected to the plus and minus terminals of the main DC power source 14. The average voltage of the motor winding terminal 52 is controlled in accordance with the ratio of the period when the winding terminal is connected to the plus terminal to the period when the winding terminal is connected to the minus terminal. Ideally speaking, when the voltage of the main DC power source 14 is fixed, the average voltage of the motor winding terminal 52 is uniquely controlled in accordance with the time ratio of `H` level to `L` level of the switching control signal 42.
In the prior art output circuit for the PWM inverter, however, there exists the floating state and hence the average voltage of the motor winding terminal 52 is varied depending on the direction of the current flowing through the motor winding terminal 52. Specifically, when the floating state is established under the state where the current flows in the direction along which the current flows from the motor winding terminal 52 into the output circuit 53 for the PWM inverter, a diode 78 conducts and hence the state where the motor winding terminal 52 is connected to the plus terminal of the main DC power source 14 is produced. This state is indicated by a terminal voltage 51A of motor winding in FIG. 11. By contrast, when the current flows in the direction along which the current flows from the output circuit 53 for the PWM inverter into the motor winding terminal 52 under the floating state, a diode 79 conducts, and hence the state where the motor winding terminal 52 is connected to the minus terminal of the main DC power source 14 is produced. This state is indicated by a terminal voltage 51B of motor winding in FIG. 11. When no current flows through the motor winding terminal 52 under the floating state, the voltage of the motor winding terminal 52 is determined by voltages such as an induced voltage generated in the motor 60.
As described above, the existence of the floating state causes the average voltage of the motor winding terminal 52 not to be uniquely determined by the switching control signal 42, thereby producing a control error. Usually, since the current passing through the motor winding terminal 52 is an alternating current and changed in the direction, the control error is also changed depending on the change of the direction of current, and thereby the torque and the rotational speed of the motor 60 are varied. This problem can be solved by eliminating the floating state and making the floating time period zero. In the conventional output circuit for the PWM inverter, however, a short circuit between the plus and minus terminals of the main power source 14 occurs and hence it is practically impossible to solve the problem.
Furthermore, when the power transistor is turned ON or OFF, electric noise is produced. In a use wherein such electric noise should be reduced in level, particularly, the switching speed is sometimes lowered by, for example, a method in which a capacitor is connected across the base and the emitter of the power transistor. However, this countermeasure increases variations of the operation delay times TX1, TX2, TY1, and TY2 to a very large value, whereby the floating time is inevitably further prolonged. Therefore, the control error is increased, with the result that the switching speed cannot be largely lowered.
Other conventional output circuits for the PWM inverter are used in which the power transistors 70 and 71 of FIG. 10 are replaced with power MOS-FETs, respectively, or in which the power transistors are replaced with IGBTs, respectively. However, also these circuits operate in the same manner as the conventional output circuit for the PWM inverter shown in FIG. 10 and has the floating state.